The present invention relates to a technology which is effective when applied to a processing technique for a gate electrode or the like in a manufacturing method of a semiconductor integrated circuit device (or semiconductor device).
Japanese Unexamined Patent Publication No. 2002-175981 (Patent Document 1) or US Patent Publication No. 2002-59557 (Patent Document 2) corresponding thereto discloses a technique in which, in the patterning of gate electrodes in a SRAM (Static Random Access Memory) or the like, in order to avoid the Rounding of pattern corner portions, the steps of patterning a resist film with respect to a hard mask film, patterning the hard mask film using the resist film, and removing the resist film are repeated twice to obtain a hard-mask-film pattern of which the corner portions are not Rounded.
Japanese Unexamined Patent Publication No. 2008-91824 (Patent Document 3) or U.S. Pat. No. 7,462,566 (Patent Document 4) corresponding thereto discloses a technique in which, in the patterning of gate electrodes or the like, after a hard mask is patterned first using a first resist film having a line & space pattern and the resist film is removed, a micropattern is transferred onto a second resist film and, using the new resist film, the hard mask is processed.
Japanese Unexamined Patent Publication No. 2010-118599 (Patent Document 5) discloses a technique in which, in the patterning of gate electrodes or the like, etching of a target film for separating gate abutment portions located over an isolation region is performed first using a first resist film and, after the resist is removed, etching of the target film is performed using a second resist film having a line & space pattern.